This invention relates to packing techniques for integrated devices and in particular to routing under connection lands using the Redistribution Layer (RDL) of a Wafer Level Chip Scale Package (WLCSP).
WLCSP is a packaging technique in which solder bumps or balls for external connections are formed on, and electrically connected to, an integrated device such as an Integrated Circuit (IC), Integrated Passive Device (IPD), Microelectro-Mechanical Systems (MEMS) device, display device, or image sensor device prior to dicing of the wafer or panel.
WLCSP devices comprise an Under Ball Metallisation (UBM) layer on the surface of the device for the formation of solder ball lands, separated from the integrated device by insulating polymer layers. An intermediate metallic RDL is provided for the definition of tracks to connect bond pads on the integrated device to solder ball lands in the UBM layer. Vias through the polymer layers provide connections between the integrated device connection points and the RDL tracks, and between the RDL tracks and the UBM solder ball lands.
FIG. 1 shows plan and cross-section views of a typical WLCSP device. IC layers 102 are formed within the wafer and a lower polymer layer 103 is deposited over the wafer. A via 104 is formed through the first polymer layer 103 to make contact between a bond pad 105 on the IC and the WLCSP RDL 106. An upper polymer layer 107 is deposited over the RDL 106. A via 108 is formed through the upper polymer layer 107 to make contact between the RDL 106 and a land 101 formed in the UBM layer. The UBM land 101 is used for the attachment of solder balls or bumps.
The via 108 between the RDL 106 and UBM land 1019 may be defined to be smaller or bigger than the solder ball land 101 and associated RDL area to provide keying of the layers into the polymer to mechanically anchor the metallic layers to the polymer and thus to the IC.
As the complexity of integrated devices increases the number of external connections required also increases thus leading to increased routing complexity in the RDL and UBM layers.
Routing problems can be addressed by increasing the number of layers (e.g. by using two RDLs), but increasing that is undesirable in this particular application as additional layers also require additional polymer layers. The deposition of polymer layers utilises a thermal process which must be considered against the thermal budget for the integrated device, thereby raising reliability considerations. Additional layers also add process steps and therefore add to the cost of each device.
There is therefore a requirement for a technique to allow improved signal routing between integrated device bond pads and solder ball lands in the UBM layer.